SMILE PROJECT

1. INTRODUCTION

Within the framework of their cooperation, Philips, MATRA MHS and SUN Microsystems, elected to contribute to the OMI/ESPRIT III European programme by developing a line of Supercells oriented to the SPARC architecture. This project is called SMILE (Sparc Macrocell Interface Library and Elements) and gather the work of about ten European companies and Universities among which the programme contractors are Philips Semiconductors, MATRA MHS, TGI and Nordic VLSI. Currently, the programme is developing around ten specific Supercells that will interface with the modular SPARC architecture developed in SMILE.

The programme is supported by application sponsors such as Disel, a Spanish company from the INI group that specializes in industrial process control, or Tandberg Telecom, from Norway, that manufactures office multimedia systems (Video Conferencing Desktop).

The Supercells will be available at the end of 1994. They will be part of a library that will be fully compatible to the EEC ELI (European Library Interface) recommendations.

Relying on a common strategy in this field, the directions given to these developments will bring solutions to the economical and technical constraints that are specific of highly integrated systems, embedded and portable. Indeed, although this market has a current yearly growth rate of more than forty percent in the Telecommunication and Office Automation segments, other applications such as multimedia, mobile communication systems and automotive are emerging.

The current developments are aiming to address, as early as 1995, several applications in telecommunication, (GSM, Visiophone,...), multimedia (PDA, Games, Interactive TV, ...), and industrial process control.

The features of the multimedia cells and the SPARC cores are fully suited to battery operated systems, such as the Personal Intelligent Communicators, where high level of integration and clever power management techniques are mandatory.

MATRA MHS and Philips have selected the SPARC architecture in making agreements with SUN Microsystems to acquire the technology of the V8/micro SPARC as the base of their developments in SMILE. Together with SMILE partners the companies are specifying a modular architecture according to two standards, which are the V8e and PI-BUS.

The SPARC architecture (SPARC International -V7-8-9, IEEEP1754) is the best-selling commercial architecture (64 % market share) of the workstation and server market segments. The architecture suits also very well open systems. As a consequence, the direction of the developments undertaken by SMILE, together with SPARC International and several European companies, will define an extension to the current V8 standard in order to improve its performance against the real time requirements of the targeted embedded system. In 1994, SPARC International will make official this new V8e standard that will be implemented in the SMILE Architecture.

2. SMILE TECHNOLOGY

The modular technology selected by SMILE is built around a new methodology for IC design. It relies on behavioral description tools and a modular/parameterizable SPARC architecture. This makes easier the integration of modules (called also Supercells) that are developed by the application partners. The manipulation of Supercells that are made of several millions of transistors is calling for the most advanced design tools in the field of behavioural description and logic synthesis. This new top-down design methodology will allow significant improvements in the design time, test time and integration of these new 32-bit microsystems. These Supercells through several levels of description will support Verilog and VHDL design environments according to the OMI/standards guidelines.

The SMILE modular architecture is organized into three parts:

The Core - A SPARC harvard integer unit style that fulfils the SPARC V8e standard, instructions and data caches whose organizations and sizes are user programmable (4/2 Kbyte, 2-ways associative, lockable, four 32-bit word per line). Two optional units, a FPU and a MMU that are compatible with the SPARC V8e specifications are also available to be integrated together with the core. Two implementations are driven by MATRA MHS and PHILIPS.

Generic peripherals - Several peripherals take place around the core: A memory interface, a counter/timer unit and a device to help to debug, test and initialize the whole circuit. The latter device allows the processor to be emulated through the use of JTAG and its serial interface.

The last category of modules is open to users that require some application specific units. These units will interface with the processor core through a standard bus (PI-BUS) that has been jointly developed following the work done by Siemens, Philips, Matra MHS, Inmos and ARM within the European OMI project (Open Microprocessor systems Initiative).

3. PROJECT STRUCTURE

The project is organized in 5 workpackages. Workpackage 1 is in charge of the development of the two SPARC cores lead by MATRA MHS and PHILIPS. Associated with these tasks the performance analysis tools developed by University of Hamburg is also a part of the WP1. Workpackage 2 is in charge of the development of the system Supercells like MMU, FPU, Caches, etc... Workpackage 3 is lead by Nordic VLSI. The goal is to develop a set of Supercells for Multimedia applications like Desktop video systems, and PDA. Workpackage 4 is lead by TGI. The objectives are to develop a Remote Unit Controller using SPARC core and Real-time Supercells.

Two demonstrators are planned during the life of the project. At the end of 94, a low-power SPARC demonstrator will be available. At the end of the SMILE project (Mid 95), a demonstrator exploiting several Supercells coming from different sources will be built.

4. ROLE OF PARTNERS

MATRA MHS/France

MATRA MHS is the prime contractor of SMILE. The main objectives of MHS are to specify and to develop a modular and high performance SPARC architecture according to the company product strategy.

The first task was to develop a new SPARC core according to several embedded applications requirements. The development of this new core consists in four parts, which are the Integer Unit, the Floating Point Unit, the Caches and the memory interface. All these parts are designed by MHS except the FPU which is developed by Meiko the English company associated with MATRA MHS in SMILE.

The specificity of the core is the capability of the architecture to process digital signal algorithms. MHS has added new instructions like Multiply and Accumulate and developed a parallel structure allowing concurrent operations (memory access, execution of instructions, multiplications, floating point processing, ....). However, these improvements are optimized in order to reduce and to achieve a small size of the core.

The modularity and parametrization are strong characteristics of the SPARC core models. All of these blocks and the associated design methodology are adapted to be exploited in a library concept. The MHS SPARC core is interfaced with the internal peripherals and application specific supercells through PI-BUS.

PHILIPS RESEARCH LABS/Netherlands

Within the OMI/SMILE project Philips is a project contractor and currently developing supercells for use in SPARC based microcontroller devices suitable for emerging markets like Personal Intelligent Communicators and Intelligent TV boxes, interactive systems and games.

Gaining low power consumption and a high integration level are important targets for development. Half-micron process technology, low voltage operation at 3.0V and a flexible supercell architecture will help to achieve these targets.

In the first phase of SMILE a modular architecture has been defined and initial versions of supercells created at Philips :

• A SPARC CPU based on SUN Microsystem's microSPARC Integer Unit design. Various enhancements for embedded/real-time control applications like fast multiplication and features from the SPARC V8e standardisation.
• Split Instruction and Data Caches allow a range of different configurations. The user of these library cells gets the choice of defining logical organisation and capacity of the cache according to the individual constraints of the application.
• An on-chip System Bus based on the OMI/PI Bus specification provides a well-defined interface between core and application microcells. This feature will allow quick integration of functional blocks from system partners.
• A Debug Support Unit using the IEEE standard JTAG bus as a communication link to a host workstation. Various hardware condition match and trace facilities are provided to allow efficient debugging of real-time code.

Currently a Demonstrator chip is in preparation showing the capabilities of the above architecture.

In addition, a fast executing algorithmic simulator covering the complete architecture is under development

in cooperation with the Universitat der Bundeswehr Hamburg.

Its application ranges from hard and software perfomance analysis to software development on a virtual target.

TGI-DISEL/Spain

TGI is a project contractor. Disel is an associated partner of TGI.

TGI represents a diversified industrial group (TENEO) interested in using the results of SMILE in the design and development of embedded electronic systems. TGI together with DISEL are developing the necessary techniques and specific components (communications, interrupt control, I/O circuitry etc...), needed to design and evaluate real time embedded applications. The design process uses a supercell oriented methodology which employs the "core" cells of the SPARC architecture that are being designed in the SMILE project. In order to evaluate the system, a complete evaluation platform that includes a commercial real-time operating system is being developed. The results are being applied on a test case consisting of the CPU of a distributed control system.

NORDIC VLSI/Norway

Within SMILE Nordic VLSI is a project contractor.

The driving application of work package 3 is the videophone, but the supercells being developed are also of general use in multimedia personal computers and work stations, personal digital assistants and similar products.

Nordic VLSI AS is a part of Tandberg AS, Tandberg Telecom AS, which is also owned by Tandberg AS, is manufacturing videophones and is the sponsor of Nordic VLSI AS in the SMILE project.

Nordic VLSI is developing supercells in cooperation with the University of Sussex and Matra Cap Systemes. All supercells communicate by PI-Bus, and are controlled by the SPARC core.

Nordic VLSI and Matra Cap Systemes will design a general decompression supercell suitable for the decompression of both JPEG and H.261 picture blocks.

The output of the decompression cell is sent to an image transforming and display supercell to be designed by the University of Sussex. This cell will reconstruct and display complete pictures from the decompressed picture blocks according to the CCITT H.261 standard. The display supercell also performs X11 and Microsoft Windows graphics operations. A wide variety of displays can be used. Any complete multimedia system will need sound processing capabilities. In work package 3.6, Nordic VLSI is developing analog-to-digital (ADC) and digital-to-analog (DAC) converters for use in sound processing.

The ADC is a sigma-delta converter, with 14 bits of resolution and a sampling frequency of 16 kHz. The ADC is a preprocessor for cells for sound compression according to CCITT standards. The DAC will be a bitstream converter running at the same speed as the ADC.

MATRA CAP SYSTEMES/France

MATRA CAP SYSTEMES is an associated partner of MATRA MHS. MCS is primarily involved in the multimedia workpackage.

MATRA CAP SYSTEMES has two main tasks:

The first one is a study the state of the art in multimedia mainly in image compression. The objectives of this task are to identify the application requirements and to specify the architecture of the image compression supercell.

The second one is, in collaboration with Nordic VLSI, to specify and design a Supercell for image decompression.

This Supercell can work with two standards in use today, JPEG and H261. The model of Supercell is written in VHDL.

UNIVERSITY OF SUSSEX /United Kingdom

University of Sussex is an associated partner of MATRA MHS.

The VLSI and Graphics Group at the University of Sussex is designing a sophisticated supercell for multimedia applications. The supercell incorporates features to support videophone, Personal Digital Assistant and window acceleration applications.

The supercell is provided with a PI-Bus interface to the host processor core and is being designed using a methodology based on VHDL and logic synthesis. It includes the control functions for a wide variety of display devices including different types of CRT and LCD panels. It will offer a range of window management, 2D drawing functions and block transfer modes with an interface to a separate display memory.

The videophone support functionality is being designed to meet the requirements of H261 and includes YUV 4:1:1 and 4:2:2 to RGB conversion.

The supercell will be a contribution to the OMI Library. In addition to the multimedia supercell the University of Sussex group has developed VHDL models of the PI-Bus control unit and the associated master and slave units. This bus is the main interface between cores and peripheral supercells in OMI.

UNIVERSITAT DER BUNDESWEHR HAMBURG/Germany.

Within SMILE the Universität der Bundeswehr Hamburg (UniBwH), Germany, acts as an associate contractor to Philips and contributes to the performance analysis part of the project (workpackage WP1.4).

With respect to embedded systems and real time applications the first task is to design and to implement a modular timed simulator for analysis runs. This simulator will model the SPARC core elements as well as the application partner specific supercells. In this context various modules of the SUN proprietary SPARC Architectural Simulator (SAS) have to be modified; UniBwH is responsible for the implementation of the complex clock cycle accurate Integer Unit module.

The second task of the UniBwH is to upgrade the simulator's functionality in order to support real time system evaluation. This means a comfortable application designer user interface for online statistical interpretation and appropriate representation of performance analysis results, e.g. instruction distribution component loads, and marking of critical areas.

As a result the modified simulation environment will provide a flexible parameter modification both of the core and - in principle - of the application specific cells, and will permit the analysis of the overall system behaviour in an easy way.

5. SUMMARY

SMILE is providing the ability to develop SPARC application oriented driving microprocessors in order to solve the price-performance-reliability equation on new solutions.

6. CONTACT INFORMATION

For further information on SMILE, contact SMILE's project Manager, Mr. Alain Fanet, MATRA MHS SA, Les Quadrants, 3 Avenue Du Centre -BP 309, 78054 Saint-Quentin-En-Yvelines Cedex, France. Phone +33-1-30607059, Fax +33-1-30640693, Email alain.fanet@matramhs.fr.